Load-link/store-conditional

Technology

Low-impact change.

Impact 27.4 · Hidden · Confidence 75

• The revision omits the prior detail about how LL/SC addresses are tracked and what exact cache-line modifications trigger a store-conditional failure, which alters the depicted mechanism of failure and could affect reader expectations about coherence behavior.

Replace “the address being accessed exclusively to be configured in write through mode Typically CPUs track the load linked address at a cache line or other granularity such that any modification to any portion of the cache line whether via another core's store conditional or merely by an ordinary store is sufficient to cause the store conditional to fail All of these platforms provide weak LL SC The PowerPC implementation allows” with “the address being accessed exclusively to be configured in write through mode All of these platforms provide weak LL SC The PowerPC implementation allows”.

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